START YOUR SYSTEM VALIDATION EARLY

 

UVM based Verification IP for HW simulation and emulation environments

 

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System Verilog
UVM based
Verification IP
for all major
HW simulators

 

 

 

X-STEP VIPs provide the same functionality than X-STEP Actor to be used in the beginning of the product process. The supported protocols are CPRI, OBSAI RP3 and JESD204. VIPs are designed and tested with major EDA vendors simulators and have three parts: UVM connection to TB with monitors, System Verilog BFM with example TBs and the C-code core, the same that is used in all X-STEP products. X-STEP VIPs gives the user a good starting point in their system validation as all tests are directly reusable with X-STEP Actor in later phases of the project.